1. Field of the Invention
The present invention relates to a charge pump circuit and a phase locked loop (PLL) circuit using a charge pump circuit, such as a PLL circuit for generating local oscillation signals in a wireless communication system and a charge pump circuit used for the same.
2. Description of Related Art
When a charge pump circuit is off, leakage current induces a voltage fluctuation of an output signal of the charge pump circuit and has become one of the causes of fluctuation in the oscillation frequency of a PLL circuit. For this reason, a reduction of the leakage current at the OFF time is an important characteristic required for the charge pump circuit. In recent years, power supply voltage has been lowered along with miniaturization of a semiconductor device, so it becomes necessary to lower a threshold voltage of a transistor for operation at a low voltage. Due to this, the leakage current at the OFF time of the transistor tends to increase.
FIG. 8 is a view showing an example of a charge pump circuit. As illustrated, this charge pump circuit is configured by nMOS transistors NT1, NT2, and NT3 and pMOS transistors PT1, PT2, and PT3. The transistors NT2 and NT3 form a differential pair circuit. The transistor NT1 is connected between a connection point of sources of the transistors NT2 and NT3 and a note of a ground potential and supplies a current to the differential operation pair circuit. Also, the transistors PT2 and PT3 form a differential operation pair circuit. The transistor PT1 is connected between the connection point of sources of the transistors PT2 and PT3 and a power supply terminal of a power supply voltage VCC and supplies the current to the differential operation pair circuit.
In the charge pump circuit, the differential operation pair circuit configured by the transistors NT2 and NT3 outputs a discharge current IDN to an output terminal OUT in accordance with a down signal DN and its logic inverted signal DNX. Namely, in accordance with the down signal DN and its logic inverted signal DNX, a pull-in current IDN flowing from the output terminal OUT to a ground potential GND is generated. On the other hand, the differential operation pair circuit configured by the transistors PT2 and PT3 outputs a charge current IUP to the output terminal OUT, in accordance with an up signal UP and its logic inverted signal UPX.
The charge pump circuit controls a current value of a discharge current IDN by a bias voltage VN supplied to the gate of the transistor NT1 and controls the current value of the charge current IUP by a bias voltage VP supplied to the gate of the transistor PT1. Further, the timing of the discharge current IDN and the charge current IUP is controlled by the down signal DN and the up signal UP, as explained above.
In the charge pump circuit, a reduction of the leakage current at the time of OFF can be achieved by enlarging the amplitudes of the up signal UP and its logic inverted signal UPX and the down signal DN and its logic inverted signal DNX. However, the current IDN and IUP flow through the transistors NT3 and PT3 also at the OFF time, so there is a problem of a large current consumption. Further, when switching the transistors NT2 and NT3 in accordance with the down signal DN and its logic inverted signal DNX or when switching the transistors PT2 and PT3 in accordance with the up signal UP and its logic inverted signal UPX, both transistors configuring the differential operation pair circuit are turned ON. For this reason, for example, when the down signal DN and its logic inverted signal DNX switch, both of the transistors NT2 and NT3 are turned ON, so the output terminal OUT and the supply side of the power supply voltage VCC are short circuited, and charges flow into the output terminal OUT. On the other hand, when the up signal UP and its logical inverted signal UPX switch, both of the transistors PT2 and PT3 are turned ON, so the output terminal OUT and the ground potential GND are short circuited, and charges flow out of the output terminal OUT.
In accordance with the inflow or outflow of the charges due to the switching of the down signal DN and the up signal UP explained above, a terminal voltage VC of a capacitor connected to the output terminal OUT of the charge pump circuit changes, so the oscillation frequency of a voltage controlled oscillator controlled by this terminal voltage VC deviates from the desired value.
In order to avoid the above problems, a charge pump circuit shown in FIG. 9 is proposed. As illustrated, in the charge pump circuit of the present example, a buffer amplifier AMP1 is provided. A positive input terminal of the buffer amplifier AMP1 is connected to the connection point of drains of the transistors NT2 and PT2, and the output terminal thereof and a negative input terminal are connected to a connection point A of drains of the transistors NT3 and PT3.
Namely, in this charge pump circuit, the buffer amplifier AMP1 configures a voltage follower. By this, the output terminal A of the buffer amplifier AMP1 is held at the same voltage as that of the positive input terminal thereof. For this reason, when switching the transistors in accordance with the down signal DN and its logic inverted signal DNX or when switching the transistors in accordance with the up signal UP and its logic inverted signal UPX, the inflow or outflow of charge current from the terminal A to the output terminal OUT can be prevented.
In the charge pump circuit shown in FIG. 9, however, the current IDN and the current IUP flow through the transistors NT3 and PT3 also at the OFF time, so the problem of large current consumption is not solved. Further, a buffer amplifier AMP1 requiring an output larger than the current IDN and the current IUP is necessary, so there are problems in that the power consumption further increases and the size of the circuit becomes large.
As related art, Japanese Unexamined Patent Publication (Kokai) No. 2001-177400, Japanese Unexamined Patent Publication (Kokai) No. 2000-269808, and “A PPL Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal of Solid-State Circuits, vol. 127, no. 11, November 1992, pp. 1599 to 1607, may be mentioned.
In order to reduce the leakage current at the OFF time in the conventional charge pump circuit explained above, a variety of measures have been taken. For example, in the charge pump circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-269808, when the current is not output, a back bias voltage is supplied to the transistor to reduce the leakage current at the OFF time.
For example, taking the circuit shown in FIG. 8 as an example, at the nMOS transistor side generating the discharge current IDN, when the current IDN is not output, a signal of a low level of, for example, the ground potential level is supplied to the gates of the transistors NT1 and NT2, and a signal of a high level of, for example, the power supply voltage VCC is supplied to the gate of the transistor NT3. Due to this, the connection point of the sources of the transistors NT2 and NT3 configuring the differential operation pair circuit is held at the high level, for example, a voltage lower than the power supply voltage VCC by exactly the amount of a gate-source voltage Vgs of the transistor NT3 (Vcc−Vgs). For this reason, a back bias voltage is supplied to the transistor NT2 to reduce the leakage current at the OFF time.
However, the signal actually determining the output timing of the discharge current IDN is the drive signal supplied to the gate of the transistor NT2. This drive signal is a switching control signal including the analog amplitude information. The current value of the current IDN is determined according to the amplitude. In general, it is difficult to raise this drive signal sharply. This is because a capacity in accordance with a load capacity is added to the gate of the transistor NT2 other than the gate capacity, so a larger drivability than the usual one is needed for driving the gate of the transistor NT2. Further, this drive signal is not a logic signal, but an analog signal also needing amplitude information, so a buffer circuit of a logic able to easily raise the drivability cannot be used.
Note that, in the charge pump circuit shown in FIG. 8, not only at the nMOS transistor side for generating the discharge current IDN, but also at the pMOS transistor side for generating the charge current IUP, similarly, the drive signal supplied to the gate of the transistor PT2 is an analog signal having amplitude information, so sharp rising is difficult due to the limitation of the drivability.
Due to the above reasons, the rising characteristic of the drive signal supplied to the gate of the transistor NT2 is poor, so it becomes impossible to drive this by a pulse signal having a short width. For this reason, in the PLL circuit connected to the output terminal OUT of the charge pump circuit, receiving the output current of the charge pump circuit, generating a control signal SC, and controlling the oscillation frequency of the voltage control oscillator (VCO) by using this control signal SC, there are the disadvantages that the precision of the control signal SC is lowered and it becomes impossible to control the oscillation frequency with a high precision.